1. Field of the Invention
The present invention relates to an arithmetic and logic operating unit, and more particularly, it relates to the structure of an arithmetic and logic operating unit which can perform AMI (Alternate Mark Inversion) coding at a high speed.
2. Description of the Prior Art
AMI coding is the technique of comparing an input A with a predetermined threshold value B (B&gt;0) by performing three-level decision of A&gt;B, .vertline.A.vertline..ltoreq.B and A&lt;-B and outputting a code responsive to the result of decision.
FIG. 1 illustrates an example of such AMI coding. Description is now concretely made on the AMI coding with reference to FIG. 1.
First, a predetermined threshold value B (where B&gt;0) is compared with the value of an external input signal A at a given time. At this time, "1" is outputted if A&gt;B, "0" is outputted if .vertline.A.vertline..ltoreq.B while "-1" is outputted if A&lt;-B. The input signal A is thus subjected to AMI coding.
There is no existing arithmetic and logic unit (ALU) which can perform the three-level decision, i.e., AMI coding in one machine cycle. THerefore, the conventional ALU has coped with AMI coding through software.
FIG. 2 is a flow chart for illustrating an exemplary flow of software processing for AMI coding through the conventional ALU. In this flow chart, the absolute value of an input signal A is first obtained (step 1). Then a threshold value B is subtracted from the absolute value of the input signal A (step 2). Then a determination is made as to whether or not the result of subtraction (.vertline.A.vertline.-B) is positive (step 3). If the result is positive, the sign of the input signal A is outputted (steps 4 and 6), while "0" is outputted if the result is not positive (steps 5 and 6). The input signal A and the threshold value B are subjected to three-level decision through the aforementioned steps, whereby AMI coding of the input signal A is performed.
When such operation is performed by a general microprogram control system through the conventional ALU, a number of machine cycles are required for executing AMI coding since a plurality of times of arithmetics and condition judgements etc. are included, whereby the operation cannot be performed at a high speed.
The general procedure for designing the arithmetic and logic unit in the background of the present invention is disclosed in "Digital Logic and Computer Design" by M. Morris Mano, Chap. 9, published by Prentice Hall, 1979, which is translated and published in Japan by Kyoritsu Shuppan.